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january 2007 hyb18l256160bcx-7.5 hyb18l256160bfx-7.5 hye18l256160bcx-7.5 hye18l256160bfx-7.5 drams for mobile applications 256-mbit mobile-ram mobile-ram data sheet rev. 1.11
data sheet 2 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram hyb18l256160bcx-7.5 hyb18l256160bfx-7.5 hye18l256160bcx-7.5 hye18l256160bfx-7.5 revision history: rev. 1.11 2007-01 all new qimonda template previous revision: rev. 1.10 , 2006-07 46 idd6 change to 2.5 ma 46 - idd7 add note 4 to indicate typical value. 6 add rohs compliant all add hye products (extended temperature range) 48 figure title: editorial change we listen to your comments any information within this do cument that you feel is wro ng, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com
data sheet 3 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram overview 1overview 1.1 features ? 4 banks 4 mbit 16 organization ? fully synchronous to positive clock edge ? four internal banks for concurrent operation ? programmable cas latency: 2, 3 ? programmable burst length: 1, 2, 4, 8 or full page ? programmable wrap sequence: sequential or interleaved ? programmable drive strength ? auto refresh and self refresh modes ? 8192 refresh cycles / 64 ms ? auto precharge ? commercial (0c to +70c) and extended (-25c to +85c) operating temperature range ? 54-ball p-vfbga package (12.0 8.0 1.0 mm) ? rohs compliant product 1) power saving features ? low supply voltages: v dd = 1.70v to 1.95v, v ddq = 1.70v to 1.95v ? optimized self refresh ( i dd6 ) and standby currents ( i dd2 / i dd3 ) ? programmable partial ar ray self refresh (pasr) ? temperature compensated self-refresh (tcsr), controlled by on-chip temperature sensor ? power-down and deep power down modes 1)rohs compliant product: restriction of the use of certain hazardous substances (rohs) in electrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include mercur y, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominat ed biphenyl ethers. table 1 performance part number speed code - 7.5 unit speed grade 133 mhz access time ( t acmax )cl = 35.4ns cl = 2 6.0 ns clock cycle time ( t ckmin )cl = 37.5ns cl = 2 9.5 ns table 2 memory addressing scheme item addresses banks ba0, ba1 rows a0 - a12 columns a0 - a8
data sheet 4 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram overview 1.2 pin configuration figure 1 standard ballout 256-mbit mobile-ram table 3 ordering information type 1) package description commercial temperature range hyb18l256160bcx-7.5 p-vfbga-54-2 133 mhz 4 banks 4 mbit 16 lp-sdram hyb18l256160bfx-7.5 p-vfbga-54-2 133 mhz 4 banks 4 mbit 16 lp-sdram extended temperature range hye18l256160bcx-7.5 p-vfbga-54-2 133 mhz 4 banks 4 mbit 16 lp-sdram hye18l256160bfx-7.5 p-vfbg a-54-2 133 mhz 4 banks 4 mbit 16 lp-sdram 1) hyb/e: designator for memory products (hyb: commercial temp. range; hye: extended temp. range) 18l: 1.8v mobile-ram 256: 256 mbit density 160: 16 bit interface width b: die revision c / f: lead-containing product (c) / green product (f) x: relaxed standby current -7.5: speed grade(s): min. clock cycle time 6 3 3 1 5 $ 1 - 6 $ $ 1 $ 1 $ 1 $ 1 6 3 3 1 6 $ $ 1 # + % # , + ! ! ! ! $ 1 $ 1 $ 1 6 3 3 " ! $ 1 $ 1 $ 1 6 $ $ , $ 1 - $ 1 6 3 3 1 6 $ $ 1 6 3 3 1 " ! ! ! ! 0 6 $ $ 6 $ $ 1 $ 1 $ 1 $ 1 $ 1 ! " # $ & ' ( * % # ! 3 2 ! 3 7 % ! ! 6 3 3 ! 6 $ $ ! ! ! $ 1 ! 6 3 3 . # $ 1 # 3
data sheet 5 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram overview 1.3 description the hy[b/e]18l256160b[c/f]x is a high-speed cm os, dynamic random-access memory containing 268,435,456 bits. it is internally configured as a quad-bank dram. the hy[b/e]18l256160b[c/f]x achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to the system clock. read and write accesses are burst-oriented; accesses start at a selected location and continue for a programmed number of locations (1, 2, 4, 8 or full page) in a programmed sequence. the device operation is fully synchronous: all inputs are registered at the positive edge of clk. the hy[b/e]18l256160b[c/f]x is especially designed for mobile applications. it operates from a 1.8v power supply. power consumption in self refresh mode is drastically reduced by an on-chip temperature sensor (octs); it can further be reduced by using the progra mmable partial array se lf refresh (pasr). a conventional data-retaining power-down (pd) mode is available as well as a non-data-retaining deep power- down (dpd) mode. the hy[b/e]18l256160b[c/f]x is housed in a 54-ball p- vfbga package. it is av ailable in commercial (0 c to 70 c) and extended (-25 c to 85 c) temperature range. figure 2 functional block diagram # + % # , + # 3 2 ! 3 # ! 3 7 % ! d d r e s s 2 e g i s t e r 2 o w ! d d r e s s - u x 2 e f r e s h # o u n t e r # o m m a n d $ e c o d e - o d e 2 e g i s t e r s # o n t r o l , o g i c " a n k 2 o w ! d d r e s s , a t c h $ e c o d e r " a n k # o l u m n , o g i c # o l u m n ! d d r e s s # o u n t e r , a t c h " a n k - e m o r y ! r r a y x x 3 e n s e ! m p l i f i e r ) / ' a t i n g $ 1 - - a s k , o g i c # o l u m n $ e c o d e r ! ! " ! " ! $ 1 $ 1 $ a t a / u t p u t 2 e g $ a t a ) n p u t 2 e g , $ 1 - 5 $ 1 - " a n k " a n k " a n k
data sheet 6 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram overview 1.4 pin definition and description table 4 pin description ball type detailed function clk input clock: all inputs are sampled on the positive edge of clk. cke input clock enable: cke high activates and cke low dea ctivates internal clock signals, device input buffers and output drivers. taking cke low pr ovides precharge power-down and self refr esh operation (all banks idle), active power- down (row active in any bank) or su spend (access in progre ss). input buffers, excluding clk and cke are disabled during power-down. input buffers, excluding cke are disabled during self refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple memory banks. cs is considered part of the command code. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dq0 - dq15 i/o data inputs/output: bi-directional data bus (16 bit) ldqm, udqm input input/output mask: input mask signal for write c ycles and output enable for read cycles. for writes, dqm acts as a data mask when high. for reads, dqm acts as an output enable and places the output buff ers in high-z state when high (two clocks latency). ldqm corresponds to the data on dq0 - dq7; udqm to the data on dq8 - dq15. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an activate, read, write or precharge command is being applied. ba0, ba1 also determine which mode register is to be loaded during a mode register set command (mrs or emrs). a0 - a12 input address inputs: a0 - a12 define the row address during an active command cycle. a0 - a8 define the column address during a r ead or write command cycle. in addition, a10 (= ap) controls auto precharge operation at the end of the burst read or write cycle. during a precharge command, a10 (= ap ) in conjunction with ba0, ba1 controls which bank(s) are to be precharged: if a1 0 is high, all four banks will be precharged regardless of the state of ba0 and ba1; if a10 is low, ba0, ba1 define the bank to be precharged. during mode register set co mmands, the address inputs hold the op- code to be loaded. v ddq supply i/o power supply: isolated power for dq output buffers for improved noise immunity: v ddq = 1.70v to 1.95v v ssq supply i/o ground v dd supply power supply: power for the core lo gic and input buffers, v dd = 1.70v to 1.95v v ss supply ground n.c. ? no connect
data sheet 7 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2 functional description the 256-mbit mobile-ram is a high-speed cmos, dynami c random-access memory containing 268,435,456 bits. it is internally configured as a quad-bank dram. read and write accesses to the mobile-ram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a pr ogrammed sequence. accesses begin with the registration of an active command, followed by a read or write co mmand. the address bits re gistered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 se lect the banks, a0 - a12 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the mobile -ram must be initialized. the following sections pr ovide detailed information covering device initialization, register defini tion, command description and device operation. 2.1 power on and initialization the mobile-ram must be powered up and initialized in a predefined manner (see figure 3 ). operational procedures other than those specifie d may result in undefined operation. figure 3 power-up sequence and mode register sets 0 o w e r u p 6 $ $ a n d # + s t a b l e , o a d - o d e 2 e g i s t e r , o a d % x t - o d e 2 e g i s t e r $ o n g t # a r e " ! , " ! ( t 2 & # t 2& # t - 2 $ t - 2$ t 2 0 ? s t # + ! l l " a n k s $ 1 ( i g h : $ 1 - " ! " ! . / 0 " ! ! # / $ % . / 0 2 ! # / $ % ! d d r e s s # / $ % . / 0 2 ! # / $ % # o m m a n d 0 2 % ! 2 & ! 2 & - 2 3 . / 0 . / 0 ! # 4 - 2 3 # , + " ! , " ! , ( , e v e l 6 $ $ 6 $ $ 1 # + %
data sheet 8 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 1. at first, device core power (vdd) and device io power (vddq) must be brought up simultaneously. typically vdd and vddq are driven from a single power converter output. assert and hold cke and dqm to a high level. 2. after v dd and v ddq are stable and cke is high, apply stable clocks. 3. wait for 200 s while issuing nop or deselect commands. 4. issue a precharge all comma nd, followed by nop or desel ect commands for at least t rp period. 5. issue two auto refresh commands, each followe d by nop or deselect commands for at least t rc period. 6. issue two mode register set commands for pr ogramming the mode register and extended mode register, each followed by nop or deselect commands for at least t mrd period; the order in which both registers are programmed is not important. programming of the extended mode register may be omitted when default values (half drive strengt h, 4 bank refresh) will be used. following these steps, the mobile-ram is ready for normal operation. 2.2 register definition 2.2.1 mode register the mode register is used to define the specific mode of operation of the mobile-ram. this definition includes the selection of a burst length (bits a0-a2), a burst type (bit a3), a cas latency (bits a4-a6), and a write burst mode (bit a9). the mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is programmed again or the devi ce loses power. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. violating either of these requirements results in unspecified operation. reserved states should not be used, as unknown operation or incompatibility with future versions may result. mr mode register definition (ba[1:0] = 00 b ) ba1ba0a12a11a10a9a8a7a6a5a4a3a2a1a0 00000wb00 cl bt bl field bits type description wb 9w write burst mode 0 burst write 1 single write cl [6:4] w cas latency 010 2 011 3 note: all other bit comb inations are reserved. bt 3w burst type 0 sequential 1 interleaved
data sheet 9 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.2.1.1 burst length read and write accesses to the mobile-ram are burst oriented, with the burst length being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4, 8 locations are available for both the sequential and interleaved burst types, and a full-page burst mode is available for the sequential burst type. when a read or write command is iss ued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, me aning that the burst wraps within the block if a boundary is reached. the block is uniquely selected by a1-a8 when t he burst length is set to two, by a2-a8 when the burst length is set to four and by a3-a8 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full page bursts wrap within the page if the boundary is reached. please note that full page bursts do not self- terminate; this implies that full-p age read or write bursts with auto precharge are not legal commands. notes 1. for a burst length of 2, a1-ai select the two-data-ele ment block; a0 selects the first access within the block. 2. for a burst length of 4, a2-ai select the four-data-elem ent block; a0-a1 select the first access within the block. 3. for a burst length of 8, a3-ai select the eight-data-ele ment block; a0-a2 select the first access within the block. 4. for a full page burst, a0-ai select the starting data element. bl [2:0] w burst length 000 1 001 2 010 4 011 8 111 full page (sequential burst type only) note: all other bit comb inations are reserved. table 5 burst definition burst length starting column address order of accesses within a burst a2 a1 a0 sequential interleaved 2 0 0 - 1 0 - 1 1 1 - 0 1 - 0 4 0 0 0 - 1 - 2 - 3 0 - 1 - 2 - 3 0 1 1 - 2 - 3 - 0 1 - 0 - 3 - 2 1 0 2 - 3 - 0 - 1 2 - 3 - 0 - 1 1 1 3 - 0 - 1 - 2 3 - 2 - 1 - 0 8 0 0 0 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 0 1 1 - 2 - 3 - 4 - 5 - 6 - 7 - 0 1 - 0 - 3 - 2 - 5 - 4 - 7 - 6 0 1 0 2 - 3 - 4 - 5 - 6 - 7 - 0 - 1 2 - 3 - 0 - 1 - 6 - 7 - 4 - 5 0 1 1 3 - 4 - 5 - 6 - 7 - 0 - 1 - 2 3 - 2 - 1 - 0 - 7 - 6 - 5 - 4 1 0 0 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 1 0 1 5 - 6 - 7 - 0 - 1 - 2 - 3 - 4 5 - 4 - 7 - 6 - 1 - 0 - 3 - 2 1 1 0 6 - 7 - 0 - 1 - 2 - 3 - 4 - 5 6 - 7 - 4 - 5 - 2 - 3 - 0 - 1 1 1 1 7 - 0 - 1 - 2 - 3 - 4 - 5 - 6 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 full page n n n cn, cn+1, cn+2, ? not supported field bits type description
data sheet 10 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 5. whenever a boundary of the block is reached within a given sequence, the following access wraps within the block. 2.2.1.2 burst type accesses within a given burst may be programmed to be eith er sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of acce sses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 5 . 2.2.1.3 read latency the read latency, or cas latency, is the delay, in clock cycles, between the registration of a read command and the availability of the first piec e of output data. the latency ca n be programmed to 2 or 3 clocks. if a read command is registered at clock edge n, and the latency is m clocks, the data will be available with clock edge n + m (for details please refer to the read command description). 2.2.1.4 write burst mode when a9 = 0, the burst length programmed via a0-a2 applies to both read and write bursts; when a9 = 1, write accesses consist of single data elements only. 2.2.1.5 extended mode register the extended mode register controls addi tional low power features of the device. these include the partial array self refresh (pasr, bits a0-a2)), the temperature compen sated self refresh (tcsr, bits a3-a4)) and the drive strength selection for the dqs (bits a5-a6). the extended mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 1) and will retain the stored informatio n until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. violatin g either of these requirements result in unspecified operation. reserved states should not be used, as unknown operation or incompatibility with future versions may result. emr extended mode register (ba[1:0] = 10 b ) ba1ba0a12a11a10a9a8a7a6a5a4a3a2a1a0 10000000 ds (tcsr) pasr field bits type description ds [6:5] w selectable drive strength 00 full drive strength 01 half drive strength (default) note: all other bit comb inations are reserved. tcsr [4:3] w temperature compensated self refresh xx superseded by on-chip temperature sensor (see text)
data sheet 11 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.2.1.6 partial array self refresh (pasr) partial array self refr esh is a power-saving feature specific to mobile rams . with pasr, self refresh may be restricted to variable portions of the total array. the selection comprises all four banks, two banks, one bank, half of one bank, and a quarter of one bank. data written to the non activa ted memory sections will get lost after a period defined by t ref (cf. table 13 ). 2.2.1.7 temperature compensated self re fresh (tcsr) with on-chip temperature sensor dram devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain the stored information. this refres h requirement heavily depends on the die temperature: high temperatures correspond to short refresh periods, and low temperatures correspond to long refresh periods. the mobile-ram is equipped with an on-chip temperatur e sensor which continuously senses the actual die temperature and adjusts the refresh period in self refres h mode accordingly. this makes any programming of the tcsr bits in the extended mode register obsolete. it also is the superior solution in terms of compatibility and power-saving, because ? it is fully compatible to all processors th at do not support the extended mode register ? it is fully compatible to all applicat ions that only write a default (worst case) tcsr value, e.g. because of the lack of an external temperature sensor ? it does not require any processor interaction for regular tcsr updates 2.2.1.8 selectable drive strength the drive strength of the dq output buffers is selectable via bits a5 and a6 and shall be set load dependent. the half drive strength is suitable for typical mobile-ram applications. pasr [2:0] w partial array self refresh 000 all banks (default) 001 1/2 array (ba1 = 0) 010 1/4 array (ba1 = ba0 = 0) 101 1/8 array (ba1 = ba0 = ra12 = 0) 110 1/16 array (ba1 = ba0 = ra12 = ra11 = 0) note: all other bit comb inations are reserved. field bits type description
data sheet 12 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.3 state diagram figure 4 state diagram 2 % ! $ 0 o w e r / n - o d e 2 e g i s t e r 3 e t 0 o w e r a p p l i e d $ e e p 0 o w e r $ o w n $ 0 $ 3 8 - 2 3 ! # 4 3 e l f 2 e f r e s h 2 % & 3 2 % & 3 8 ) d l e $ 0 $ 3 ! u t o 2 e f r e s h 2 % & ! ! c t i v e 0 o w e r $ o w n # + % ( # + % , 2 o w ! c t i v e 7 2 ) 4 % 2 % ! $ 7 2 ) 4 % ! 2 % ! $ ! 0 r e c h a r g e 2 % ! $ 2 % ! $ ! 7 2 ) 4 % ! 2 % ! $ ! 7 2 ) 4 % ! 0 2 % 2 % ! $ ! 0 2 % ! u t o m a t i c 3 e q u e n c e # o m m a n d 3 e q u e n c e # l o c k 3 u s p e n d 2 % ! $ # l o c k 3 u s p e n d 2 % ! $ ! # l o c k 3 u s p e n d 7 2 ) 4 % # l o c k 3 u s p e n d 7 2 ) 4 % ! " 3 4 " 3 4 # + % , # + % , # + % , # + % , # + % ( # + % ( # + % ( # + % ( 0 2 % ! , , 0 r e c h a r g e ! l l " a n k s 2 % & 3 % n t e r 3 e l f 2 e f r e s h 2 % & 3 8 % x i t 3 e l f 2 e f r e s h 2 % & ! ! u t o 2 e f r e s h $ 0 $ 3 % n t e r $ e e p 0 o w e r $ o w n $ 0 $ 3 8 % x i t $ e e p 0 o w e r $ o w n # + % , % n t e r 0 o w e r $ o w n # + % ( % x i t 0 o w e r $ o w n 2 % ! $ 2 e a d w o ! u t o 0 r e c h a r g e 2 % ! $ ! 2 e a d w i t h ! u t o 0 r e c h a r g e 7 2 ) 4 % 7 r i t e w o ! u t o 0 r e c h a r g e 7 2 ) 4 % ! 7 r i t e w i t h ! u t o 0 r e c h a r g e 0 r e c h a r g e ! l l 0 2 % ! , , # + % , # + % ( 0 r e c h a r g e 0 o w e r $ o w n 7 2 ) 4 % 7 2 ) 4 % ! 7 2 ) 4 % 0 2 % 0 2 % ! # 4 ! c t i v e 0 2 % 0 r e c h a r g e " 3 4 " u r s t 4 e r m i n a t e - 2 3 - o d e 2 e g i s t e r 3 e t
data sheet 13 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4 commands address (a0 - a12, ba0, ba1), write data (dq0 - dq15) and command inputs (cke, cs , ras , cas , we , dqm) are all registered on the positive edge of clk. figure 5 shows the basic timing parameters, which apply to all commands and operations. figure 5 address / command inputs timing parameters table 6 command overview command cs ras cas we dqm address notes nop deselect h x x x x x 1) 1) deselect and nop are functionally interchangeable. no operation l h h h x x 1) act active (select bank and row) l l h h x bank / row 2) 2) ba0, ba1 provide bank address, and a0 - a12 provide row address. rd read (select bank and column and start read burst) l h l h l/h bank / col 3) 3) ba0, ba1 provide bank address, a0 - a8 provide column address; a10 high enab les the auto precharge feature (non persistent), a10 low disables the auto precharge feature. wr write (select bank and column and start write burst) l h l l l/h bank / col 3) bst burst terminate or deep power down lh h l x x 4) 4) this command is burst terminate if cke is high, deep power down if cke is low. the burst terminate command is defined for read or write bursts with auto precharge disabled only. pre precharge (deactivate row in bank or banks) l l h l x code 5) 5) a10 low: ba0, ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0, ba1 are ?don?t care?. arf auto refresh or self refresh (enter self refresh mode) ll lh x x 6)7) 6) this command is auto refresh if cke is high, self refresh if cke is low. 7) internal refresh counter controls row and bank addressi ng; all inputs and i/os are ?don?t care? except for cke. mrs mode register set l l l l x op-code 8) 8) ba0, ba1 select either the mode register (ba0 = 0, ba1 = 0) or the extended mode register (ba0 = 0, ba1 = 1); other combinations of ba0, ba1 are reserved; a0 - a12 provide the op-code to be written to the selected mode register. ? data write / output enable ? ? ? ? l ? 9) 9) dqm low: data present on dq s is written to memory during write cycles ; dq output buffers are enabled during read cycles; dqm high: data present on dqs are masked and thus not wri tten to memory during write cyc les; dq output buffers are placed in high-z state (two clocks late ncy) during read cycles. ? write mask / output disable (high-z) ? ? ? ? h ? 9) $ o n g t # a r e t # , t # ( t ) 3 t ) ( t # + # , + ) n p u t
6 a l i d 6 a l i d 6 a l i d
! ! " ! " ! # 3 # + % 2 ! 3 # ! 3 7 %
data sheet 14 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4.1 no operation (nop) figure 6 no operation command the no operation (nop ) command is used to perform a nop to a mobile-r am which is selected (cs = low). this prevents unwanted commands from being registered during idle states. operations already in progress are not affected. 2.4.2 deselect the deselect function (cs = high) prevents new commands from being executed by the mobile-ram. the mobile-ram is effectively deselected. operations already in progress are not affected. table 7 inputs timing parameters parameter symbol - 7.5 unit notes min. max. clock cycle time cl = 3 t ck 7.5 ? ns ? cl = 2 9.5 ? ns clock frequency cl = 3 f ck ? 133 mhz ? cl = 2 ? 105 mhz clock high-level width t ch 2.5 ? ns ? clock low-level width t cl 2.5 ? ns ? address and command input setup time t is 1.5 ? ns ? address and command input hold time t ih 0.5 ? ns ? $ o n g t # a r e 7 % # ! 3 # 3 # + % ( i g h # , + ! ! " ! " ! 2 ! 3
data sheet 15 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4.3 mode register set figure 7 mode register set command the mode register and extended mode register are loaded via inputs a0 - a12 (see mode register descriptions in chapter 2.2 ). the mode register set command can only be issued when all banks are idle and no bursts are in progress. a subsequent executable command cann ot be issued until t mrd is met. figure 8 mode register definition $ o n g t # a r e # 3 # + % ( i g h # , + ! ! # o d e " ! " ! # o d e 7 % # ! 3 2 ! 3 table 8 timing parameters fo r mode register set command parameter symbol - 7.5 units notes min. max. mode register set command period t mrd 2? t ck ? # o d e - o d e 2 e g i s t e r % x t e n d e d - o d e 2 e g i s t e r s e l e c t i o n " ! " ! a n d o p c o d e ! ! t - 2 $ $ o n g t # a r e # , + # o m m a n d - 2 3 . / 0 6 a l i d ! d d r e s s # o d e 6 a l i d
data sheet 16 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4.4 active figure 9 active command before any read or write commands can be issued to a bank within the mobile-ram, a row in that bank must be ?opened? (activated). this is accomplished via the active command and addresses a0 - a12, ba0 and ba1 (see figure 9 ), which decode and select both the bank and the row to be activated. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active commands to the same bank is defined by t rc . a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval be tween successive active commands to different banks is defined by t rrd . figure 10 bank activate timings $ o n g t # a r e " ! " a n k ! d d r e s s 2 ! 2 o w ! d d r e s s " ! " ! " ! ! ! 2 ! 7 % # ! 3 2 ! 3 # 3 # + % ( i g h # , + table 9 timing paramete rs for active command parameter symbol - 7.5 units notes min. max. active to active command period t rc 67 ? ns 1) 1) these parameters account for the number of clock c ycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. active to read or write delay t rcd 19 ? ns 1) active bank a to active bank b delay t rrd 15 ? ns 1) t 2 2 $ t 2 # $ $ o n g t # a r e # , + 2 $ 7 2 . / 0 . / 0 . / 0 ! # 4 . / 0 ! # 4 # o m m a n d 2 / 7 2 / 7 # / , ! ! " ! x " ! y " ! y " ! " !
data sheet 17 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4.5 read figure 11 read command subsequent to programming the mode register with cas latency and burst length, read bursts are initiated with a read command, as shown in figure 11 . basic timings for the dqs are shown in figure 12 ; they apply to all read operations and therefore are omitted from all subsequent timing diagrams. the starting column and bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed starts precharge at the completion of the burst, provided t ras has been satisfied. for the generic read commands used in the following illust rations, auto precharge is disabled. figure 12 basic read timing parameters for dqs " ! " ! " ! 7 % # + % ( i g h # , + 2 ! 3 # ! 3 ! ! # ! $ o n g t # a r e " ! " a n k ! d d r e s s # ! # o l u m n ! d d r e s s ! 0 ! u t o 0 r e c h a r g e ! ! 0 $ i s a b l e ! 0 % n a b l e ! 0 # 3 t , : t ! # t ! # t ( : # , + $ o n g t # a r e t $ 1 : t / ( t / ( $ 1 - $ 1 $ / n $ / n
data sheet 18 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description during read bursts, the valid data-out element from th e starting column address is available following the cas latency after the read command. each subsequent data-out element is valid nominally at the next positive clock edge. upon completion of a read burst, assuming no other read command has been initiated, the dqs go to high-z state. figure 13 and figure 14 show single read bursts for each supported cas latency setting. figure 13 single read burst (cas latency = 2) table 10 timing parameters for read parameter symbol - 7.5 units notes min. max. access time from clk cl = 3 t ac ?5.4ns? cl = 2 t ac ?6.0ns dq low-impedance time from clk t lz 1.0 ? ns ? dq high-impedance time from clk t hz 3.0 7.0 ns data out hold time t oh 2.5 ? ns ? dqm to dq high-z delay (read commands) t dqz ?2 t ck ? active to active command period t rc 67 ? ns 1) active to read or write delay t rcd 19 ? ns 1) active to precharge command period t ras 45 100k ns 1) precharge command period t rp 19 ? ns 1) 1) these parameters account for the number of clock c ycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. " a ! # o l n b a n k ! c o l u m n n $ / n $ a t a / u t f r o m c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ / n $ o n g t # a r e # , t 2 # $ t 2 ! 3 t 2 # t 20 # , + # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 0 2 % . / 0 ! # 4 ! # 4 ! d d r e s s " a ! 2 o w b " a ! # o l n " a ! 2 o w x ! ! 0 0 r e " a n k ! 0 r e ! l l $ i s ! 0 2 o w x 2 o w b ! 0 $ / n $ / n $ / n $ / n $ 1 ! 0 ! u t o 0 r e c h a r g e $ i s ! 0 $ i s a b l e ! u t o 0 r e c h a r g e
data sheet 19 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description figure 14 single read burst (cas latency = 3) data from any read burst may be concatenated with data from a subsequent read command. in either case, a continuous flow of data can be maintained. a read command can be initiated on any clock cycle following a previous read command, and may be performed to the same or a different (active) bank. the first data element from the new burst follows either the last element of a completed burst ( figure 15 ) or the last desired data element of a longer burst which is being truncated ( figure 16 ). the new read command shou ld be issued x cycles after the first read command, where x equal s the number of desired data elements. figure 15 consecutive read bursts " a ! # o l n b a n k ! c o l u m n n $ / n $ a t a / u t f r o m c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ / n $ o n g t # a r e # , t 2 # $ t 2 0 t 2 ! 3 t 2# # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 0 2 % . / 0 ! # 4 ! # 4 . / 0 . / 0 # , + ! 0 ! u t o 0 r e c h a r g e $ i s ! 0 $ i s a b l e ! u t o 0 r e c h a r g e ! d d r e s s ! ! 0 0 r e " a n k ! 0 r e ! l l $ i s ! 0 $ 1 $ / n $ / n $ / n $ / n " a ! 2 o w b 2 o w b " a ! 2 o w x 2 o w x " a ! # o l n ! 0 " a ! # o l n b " a n k ! # o l u m n n b $ / n b $ a t a / u t f r o m c o l u m n n b " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ / n b $ o n g t # a r e # , + # , # , # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 . / 0 . / 0 2 % ! $ . / 0 ! d d r e s s " a ! # o l b " a ! # o l n $ 1 $ / n $ / n $ / n $ / n $ / b $ / b $ / b $ 1 $ / n $ / n $ / n $ / n $ / b $ / b
data sheet 20 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description figure 16 random read bursts non-consecutive read bursts are shown in figure 17 . figure 17 non-consecutive read bursts " a ! # o l n e t c " a n k ! # o l u m n n e t c $ / n e t c $ a t a / u t f r o m c o l u m n n e t c " u r s t , e n g t h i n t h e c a s e s h o w n b u r s t s a r e t e r m i n a t e d b y c o n s e c u t i v e 2 % ! $ c o m m a n d s s u b s e q u e n t e l e m e n t s o f $ a t a / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ / m $ o n g t # a r e # , + # , # , # o m m a n d 2 % ! $ . / 0 . / 0 . / 0 . / 0 2 % ! $ 2 % ! $ 2 % ! $ . / 0 " a ! # o l n " a ! # o l a " a ! # o l x " a ! # o l m ! d d r e s s $ 1 $ / m $ / m $ / a $ / n $ / x $ / m $ / m $ 1 $ / m $ / a $ / n $ / x $ / m $ / m " a ! # o l n b " a n k ! # o l u m n n b $ / n b $ a t a / u t f r o m c o l u m n n b " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ / n b # , # , $ o n g t # a r e # , + # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 . / 0 . / 0 2 % ! $ . / 0 " a ! # o l n ! d d r e s s " a ! # o l b $ 1 $ / n $ / n $ / n $ / n $ / b $ / b $ 1 $ / n $ / n $ / n $ / n $ / b
data sheet 21 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4.5.1 read burst termination data from any read burst may be truncated using the burst terminate command (see page 30 ), provided that auto precharge was not activate d. the burst terminate latency is eq ual to the cas latency, i.e. the burst terminate command must be issued x clock cycles before the clock edge at wh ich the last desired data element is valid, where x equals the cas laten cy for read bursts minus 1. this is shown in figure 18 . the burst terminate command may be used to terminate a full-page read which does not self-terminate. figure 18 terminating a read burst 2.4.5.2 clock suspend mode for read cycles clock suspend mode allows to extend any read burst in progress by a variable number of clock cycles. as long as cke is registered low, the following internal clock pulse(s) will be ignor ed and data on dq will remain driven, as shown in figure 19 . figure 19 clock suspend mode for read bursts " a ! # o l n " a n k ! # o l u m n n $ / n $ a t a / u t f r o m c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ / n 4 h e b u r s t i s t e r m i n a t e d a f t e r t h e r d d a t a e l e m e n t $ o n g t # a r e # , + # , # , # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 . / 0 . / 0 " 3 4 . / 0 ! d d r e s s " a ! # o l n $ 1 $ / n $ / n $ / n $ 1 $ / n $ / n $ / n " a ! # o l n e t c " a n k ! # o l u m n n e t c $ / n e t c $ a t a / u t f r o m c o l u m n n e t c # , i n t h e c a s e s h o w n # l o c k s u s p e n d l a t e n c y t # 3 , i s c l o c k c y c l e $ o n g t # a r e # , + t # 3 , t # 3 , t # 3 , # + % i n t e r n a l c l o c k # o m m a n d 2 % ! $ . / 0 . / 0 . / 0 . / 0 . / 0 " a ! # o l n ! d d r e s s $ 1 $ / n $ / n $ / n $ / n
data sheet 22 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4.5.3 read - dqm operation dqm may be used to suppress read data and place the output buffers into high-z state. the generic timing parameters as listed in table 10 also apply to this dqm operation. the read burst in progress is not affected and will continue as programmed. figure 20 read burst - dqm operation 2.4.5.4 read to write a read burst may be followed by or truncated with a write command. the write command can be performed to the same or a different (active) bank. care must be ta ken to avoid bus contention on the dqs; therefore it is recommended that the dqs are held in high-z state for a mi nimum of 1 clock cycle. this can be achieved by either delaying the write command, or suppre ssing the data-out from the read by pulling dqm high two clock cycles prior to the write command, as shown in figure 21 . with the registration of the write command, dqm acts as a write mask: when asserted h igh, input data will be masked and no write will be performed. figure 21 read to write timing " a ! # o l n b a n k ! c o l u m n n $ / n $ a t a / u t f r o m c o l u m n n # , i n t h e c a s e s h o w n $ 1 - r e a d l a t e n c y t $ 1 : i s c l o c k c y c l e s $ o n g t # a r e # , + # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 $ 1 - t $ 1 : ! d d r e s s " a ! # o l n $ 1 $ / n $ / n $ / n " a ! # o l n b b a n k ! c o l u m n n b $ / n $ a t a / u t f r o m c o l u m n n $ ) b $ a t a ) n t o c o l u m n b $ 1 - i s a s s e r t e d ( ) ' ( t o s e t $ 1 s t o ( i g h : s t a t e f o r c l o c k c y c l e p r i o r t o t h e 7 2 ) 4 % c o m m a n d $ o n g t # a r e # , + # , # , # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 . / 0 . / 0 7 2 ) 4 % ! d d r e s s " a ! # o l b " a ! # o l n $ 1 - $ 1 $ / n $ ) b $ ) b $ / n ( i g h : $ ) b $ 1 $ ) b $ ) b $ / n ( i g h : $ ) b
data sheet 23 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4.5.5 read to precharge a read burst may be followed by, or truncated with a precharge command to the same bank, provided that auto precharge was not activated. this is shown in figure 22 . the precharge command should be issued x clock cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency for read bursts minus 1. following the precharge command, a subsequent active command to the same bank cannot be issued until t rp is met. please note that part of the row precharge time is hidden during the access of the last data elements. in the case of a read being execut ed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that woul d result from the same read burst with auto precharge enabled. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to i ssue the command. the advantage of the precharge command is that it can be used to truncate bursts. figure 22 read to precharge timing " a ! # o l n b a n k ! c o l u m n n " ! ! m 2 o w b a n k ! r o w x $ / n $ a t a / u t f r o m c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n # ! 3 l a t e n c y i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ / n $ o n g t # a r e # , # , + t 2 0 # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 . / 0 ! # 4 0 2 % " a ! 2 o w a ! d d r e s s " a ! " a ! # o l n $ i s ! 0 0 r e " a n k ! 0 r e ! l l ! ! 0 ! 0 $ 1 $ / n $ / n $ / n $ / n
data sheet 24 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4.6 write figure 23 write command write bursts are initiated with a write command, as shown in figure 23 . basic timings for the dqs are shown in figure 24 ; they apply to all write operations. the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the write burst. for the generic write commands used in the following illustrations, auto pr echarge is disabled. figure 24 basic write timi ng parameters for dqs during write bursts, the first vali d data-in element is registered co incident with the write command, and subsequent data elements are registered on each successive positive edge of clk. upon completion of a burst, assuming no other commands have been initiated, the dqs remain in high-z state, and any additional input data is ignored. figure 25 and figure 26 show a single write burst for each supported cas latency setting. " ! " ! " ! # 3 # + % ( i g h # , + 2 ! 3 # ! 3 ! ! # ! $ o n g t # a r e " ! " a n k ! d d r e s s # ! # o l u m n ! d d r e s s ! 0 ! u t o 0 r e c h a r g e ! ! 0 $ i s a b l e ! 0 % n a b l e ! 0 7 % # , + $ o n g t # a r e t ) 3 t ) ( t ) 3 t ) ( $ 1 - $ 1 $ ) n $ ) n
data sheet 25 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description figure 25 write burst (cas latency = 2) table 11 timing parameters for write parameter symbol - 7.5 units notes min. max. dq and dqm input setup time t is 1.5 ? ns ? dq input hold time t ih 0.8 ? ns ? dqm input hold time 0.5 ? ns ? dqm write mask latency t dqw 0? t ck ? active to active command period t rc 67 ? ns 1) active to read or write delay t rcd 19 ? ns 1) active to precharge command period t ras 45 100k ns 1) write recovery time t wr 14 ? ns 1) precharge command period t rp 19 ? ns 1) 1) these parameters account for the number of clock c ycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. " a ! # o l n b a n k ! c o l u m n n $ ) n $ a t a ) n t o c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n $ o n g t # a r e # , + t 2 # $ t 2 ! 3 t 2 # t 20 t 7 2 # o m m a n d . / 0 7 2 ) 4 % . / 0 . / 0 . / 0 0 2 % . / 0 ! # 4 ! # 4 . / 0 ! d d r e s s " a ! 2 o w x " a ! # o l n " a ! 2 o w b 2 o w x 2 o w b $ i s ! 0 ! 0 0 r e " a n k ! 0 r e ! l l ! ! 0 $ 1 $ ) n $ ) n $ ) n $ ) n
data sheet 26 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description figure 26 write burst (cas latency = 3) data for any write burst may be conc atenated with or truncated with a subsequent write command. in either case, a continuous flow of input data can be maintai ned. a write command can be issued on any positive edge of clock following the previous write command. the first da ta element from the new burst is applied after either the last element of a completed burst ( figure 27 ) or the last desired data element of a longer burst which is being truncated ( figure 28 ). the new write command should be issu ed x cycles after the first write command, where x equals the number of desired data elements. figure 27 consecutive write bursts " a ! # o l n b a n k ! c o l u m n n $ ) n $ a t a ) n t o c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n $ o n g t # a r e t 2 # $ t 2 ! 3 t 2 # t 2 0 t 7 2 # , + # o m m a n d . / 0 7 2 ) 4 % . / 0 . / 0 . / 0 0 2 % . / 0 ! # 4 ! # 4 . / 0 . / 0 . / 0 ! d d r e s s " a ! 2 o w n " a ! # o l n " a ! 2 o w b 0 r e " a n k ! 0 r e ! l l 2 o w x $ i s ! 0 ! 0 2 o w b ! ! 0 $ 1 $ ) n $ ) n $ ) n $ ) n " a ! # o l n b " a n k ! # o l u m n n b $ ) n b $ a t a ) n t o c o l u m n n b " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n b # o m m a n d . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 7 2 ) 4 % 7 2 ) 4 % # , + ! d d r e s s " a ! # o l b " a ! # o l n $ 1 $ ) n $ ) n $ ) n $ ) n $ ) b $ ) b $ ) b $ ) b $ o n g t # a r e
data sheet 27 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description figure 28 random write bursts non-consecutive write bursts are shown in figure 29 . figure 29 non-consecutive write bursts 2.4.6.1 write burst termination data from any write burst may be truncated using the burst terminate command (see page 30 ), provided that auto precharge was not activated. the input da ta provided coincident with the burst terminate command will be ignored. this is shown in figure 30 . the burst terminate command may be used to terminate a full-page write whic h does not self-terminate. " a ! # o l n e t c " a n k ! # o l u m n n e t c $ ) n e t c $ a t a ) n t o c o l u m n n e t c " u r s t , e n g t h i n t h e c a s e s h o w n b u r s t s a r e t e r m i n a t e d b y c o n s e c u t i v e 7 2 ) 4 % c o m m a n d s s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) m $ o n g t # a r e # , + # o m m a n d . / 0 . / 0 . / 0 . / 0 . / 0 7 2 ) 4 % 7 2 ) 4 % 7 2 ) 4 % 7 2 ) 4 % ! d d r e s s " a ! # o l m " a ! # o l x " a ! # o l a " a ! # o l n $ 1 $ ) n $ ) a $ ) x $ ) m $ ) m $ ) m $ ) m " a ! # o l n b " a n k ! # o l u m n n b $ ) n b $ a t a ) n t o c o l u m n n b " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n b $ o n g t # a r e # , + 7 2 ) 4 % # o m m a n d . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 . / 0 7 2 ) 4 % " a ! # o l n ! d d r e s s " a ! # o l b $ ) b $ 1 $ ) n $ ) n $ ) n $ ) n $ ) b $ ) b
data sheet 28 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description figure 30 terminating a write burst 2.4.6.2 clock suspend mode for write cycles clock suspend mode allows to extend any write burst in progress by a variable number of clock cycles. as long as cke is registered low, the follo wing internal clock pulse(s) will be ig nored and no data will be captured, as shown in figure 31 . figure 31 clock suspend mode for write bursts " a ! # o l n " a n k ! # o l u m n n $ ) n $ a t a ) n t o c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e w r i t t e n i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n 4 h e b u r s t i s t e r m i n a t e d a f t e r t h e r d d a t a e l e m e n t $ o n g t # a r e # , + # o m m a n d . / 0 . / 0 " 3 4 . / 0 . / 0 7 2 ) 4 % . / 0 ! d d r e s s " a ! # o l n $ 1 $ ) n $ ) n $ ) n " a ! # o l n e t c " a n k ! # o l u m n n e t c $ / n e t c $ a t a / u t f r o m c o l u m n n e t c # , i n t h e c a s e s h o w n # l o c k s u s p e n d l a t e n c y t # 3 , i s c l o c k c y c l e # , + # + % i n t e r n a l c l o c k # o m m a n d . / 0 . / 0 . / 0 7 2 ) 4 % . / 0 " a ! # o l n ! d d r e s s $ 1 $ ) n $ ) n $ ) n $ o n g t # a r e t # 3 , t # 3 , t # 3 ,
data sheet 29 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4.6.3 write - dqm operation dqm may be used to mask write data: when assert ed high, input data will be masked and no write will be performed. the generic timing parameters as listed in table 11 also apply to this dqm operation. the write burst in progress is not affected a nd will continue as programmed. figure 32 write burst - dqm operation 2.4.6.4 write to read a write burst may be followed by, or truncated with a read command. the read command can be performed to the same or a different (active) bank. with the regi stration of the read command , data inputs will be ignored and no write will be performed, as shown in figure 33 . figure 33 write to read timing " a ! # o l n " a n k ! # o l u m n n $ ) n $ a t a ) n t o c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n w i t h t h e f i r s t e l e m e n t $ ) n b e i n g m a s k e d $ 1 - w r i t e l a t e n c y i s c l o c k c y c l e s $ o n g t # a r e # , + # o m m a n d . / 0 . / 0 . / 0 . / 0 . / 0 7 2 ) 4 % ! d d r e s s " a ! # o l n $ 1 - $ 1 $ ) n $ ) n $ ) n " a ! # o l n b b a n k ! c o l u m n n b $ ) n $ a t a ) n t o c o l u m n n $ / b $ a t a / u t f r o m c o l u m n b " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n / u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n $ / b $ ) n i s i g n o r e d d u e t o 2 % ! $ c o m m a n d . o $ 1 - m a s k i n g r e q u i r e d a t t h i s p o i n t $ o n g t # a r e # , + 7 r i t e d a t a a r e i g n o r e d # , # , # o m m a n d . / 0 2 % ! $ . / 0 . / 0 . / 0 . / 0 . / 0 7 2 ) 4 % ! d d r e s s " a ! # o l b " a ! # o l n $ 1 $ / b $ / b $ / b $ ) n $ ) n $ ) n ( i g h : $ 1 $ / b $ ) b $ ) n $ ) n $ ) n ( i g h :
data sheet 30 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4.6.5 write to precharge a write burst may be followed by, or truncated with a precharge command to the same bank, provided that auto precharge was not activated. this is shown in figure 34 . the precharge command should be issued t wr after the clock edge at which the last desired data element of the write burst was registered. additi onally, when truncating a write burst, dqm must be pulled to mask input data presented during t wr prior to the precharge command. following the pre-charge command, a subsequent active command to the same bank cannot be issued until t rp is met. in the case of a write being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same write burst with auto precharge enabled. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to i ssue the command. the advantage of the precharge command is that it can be used to truncate bursts. figure 34 write to precharge timing 2.4.7 burst terminate figure 35 burst terminate command the burst terminate command is used to truncate read or write bursts (with auto precharge disabled). the most recently registered read or write command prior to the burst terminate command will be truncated, as shown in figure 18 and figure 30 , respectively. the burst terminate comma nd is not allowed for truncation of read or write bursts with auto precharge enabled. " a ! # o l n b a n k ! c o l u m n n $ ) n $ a t a ) n t o c o l u m n n " u r s t , e n g t h i n t h e c a s e s h o w n s u b s e q u e n t e l e m e n t s o f $ a t a ) n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g $ ) n $ ) n i s m a s k e d d u e t o $ 1 - p u l l e d ( ) ' ( d u r i n g t 7 2 p e r i o d p r i o r t o 0 2 % # ( ! 2 ' % c o m m a n d $ o n g t # a r e $ 1 $ ) n $ ) n $ ) n t 2 0 t 7 2 # , + $ 1 - # o m m a n d . / 0 . / 0 . / 0 . / 0 . / 0 ! # 4 0 2 % 7 2 ) 4 % ! d d r e s s " a ! # o l n " a ! 2 o w a " a ! $ i s ! 0 0 r e " a n k ! 0 r e ! l l ! ! 0 ! 0 ! 0 ! u t o 0 r e c h a r g e $ i s ! 0 $ i s a b l e ! u t o 0 r e c h a r g e $ o n g t # a r e # ! 3 # 3 # + % ( i g h # , + ! ! " ! " ! 7 % 2 ! 3
data sheet 31 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4.8 precharge figure 36 precharge command the precharge command is used to deactivate (close) the open row in a particular bank or the open row in all banks. the bank( s) will be available for a subsequent row access a specified time ( t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care?. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command will be treated as a nop if there is no open row in that bank, or if the pr eviously open row is already in the process of precharging. 2.4.8.1 auto precharge auto precharge is a feature which performs the same in dividual-bank precharge func tions described above, but without requiring an explicit command. this is accomplished by using a 10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is add ressed with the read or write command is automatically performed upon completi on of the read or write burst. auto precharge is non persistent in that it is eith er enabled or disabled for each indi vidual read or write command. auto precharge ensures that the precharge is initiated at the earliest va lid stage within a burst. the user must not issue another command to the same bank until the precharge ( t rp ) is completed. this is de termined as if an explicit precharge command was issued at the earliest possible time, as descr ibed for each burst type. " ! " ! " ! # 3 # + % ( i g h # , + $ o n g t # a r e " ! " a n k ! d d r e s s i f ! , o t h e r w i s e $ o n g t # a r e 2 ! 3 # ! 3 7 % ! / n e " a n k ! l l " a n k s ! ! ! ! table 12 timing parameters for precharge parameter symbol - 7.5 units notes min. max. active to precharge command period t ras 45 100k ns 1) 1) these parameters account for the number of clock c ycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. write recovery time t wr 14 ? ns 1) precharge command period t rp 19 ? ns 1)
data sheet 32 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4.8.2 concurrent auto precharge a read or write burst with auto pr echarge enabled can be interrupted by a subsequent read or write command issued to a different bank. figure 37 shows a read with auto precharge to bank n, inte rrupted by a read (with or without auto precharge) to bank m. the read to bank m will interrupt the read to bank n, cas latency later. the precharg e to bank n will begin when the read to bank m is registered. figure 38 shows a read with auto precharge to bank n, inte rrupted by a write (with or without auto precharge) to bank m. the precharge to bank n will begin when th e write to bank m is regi stered. dqm should be pulled high two clock cycles prior to the write to prevent bus contention. figure 39 shows a write with auto precharge to bank n, in terrupted by a read (with or without auto precharge) to bank m. the precha rge to bank n will begin t wr after the new command to bank m is registered. the last valid data-in to bank n is one clock cycle prior to the read to bank m. figure 40 shows a write with auto precharge to bank n, interrupted by a write (with or without auto precharge) to bank m. the prec harge to bank n will begin t wr after the write to bank m is registered. the last valid data-in to bank n is one clo ck cycle prior to the write to bank m. figure 37 read with auto precharge interrupted by read figure 38 read with auto precharge interrupted by write 2 $ ! 0 2 e a d w i t h ! u t o 0 r e c h a r g e 2 % ! $ 2 e a d w i t h o r w i t h o u t ! u t o 0 r e c h a r g e # , a n d " u r s t , e n g t h i n t h e c a s e s h o w n 2 e a d w i t h ! u t o 0 r e c h a r g e t o b a n k n i s i n t e r r u p t e d b y s u b s e q u e n t 2 e a d t o b a n k m $ o n g t # a r e # , # , + # o m m a n d 2 $ ! 0 . / 0 . / 0 . / 0 2 % ! $ . / 0 . / 0 . / 0 ! d d r e s s " a n k n # o l b " a n k m # o l x $ 1 $ / b $ / b $ / x $ / x $ / x t 20 b a n k n 2 $ ! 0 2 e a d w i t h ! u t o 0 r e c h a r g e 7 2 ) 4 % 7 r i t e w i t h o r w i t h o u t ! u t o 0 r e c h a r g e # , a n d " u r s t , e n g t h i n t h e c a s e s h o w n 2 e a d w i t h ! u t o 0 r e c h a r g e t o b a n k n i s i n t e r r u p t e d b y s u b s e q u e n t 7 r i t e t o b a n k m $ o n g t # a r e # , $ 1 - # , + # o m m a n d . / 0 2 $ ! 0 . / 0 . / 0 . / 0 . / 0 7 2 ) 4 % . / 0 ! d d r e s s " a n k m # o l x " a n k n # o l b $ 1 $ / b $ ) x $ ) x $ ) x $ ) x t 20 b a n k n
data sheet 33 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description figure 39 write with auto precharge interrupted by read figure 40 write with auto precharge interrupted by write 7 2 ! 0 7 r i t e w i t h ! u t o 0 r e c h a r g e 2 % ! $ 2 e a d w i t h o r w i t h o u t ! u t o 0 r e c h a r g e # , a n d " u r s t , e n g t h i n t h e c a s e s h o w n 7 r i t e w i t h ! u t o 0 r e c h a r g e t o b a n k n i s i n t e r r u p t e d b y s u b s e q u e n t 2 e a d t o b a n k m $ o n g t # a r e # , + # o m m a n d . / 0 . / 0 . / 0 2 % ! $ . / 0 ! d d r e s s " a n k n # o l b " a n k m # o l x . / 0 . / 0 7 2 ! 0 t 7 2 b a n k n t 20 b a n k n $ 1 $ / x $ / x $ / x $ / b $ / b $ / x # , 7 2 ! 0 7 r i t e w i t h ! u t o 0 r e c h a r g e 7 2 ) 4 % 7 r i t e w i t h o r w i t h o u t ! u t o 0 r e c h a r g e " u r s t , e n g t h i n t h e c a s e s h o w n 7 r i t e w i t h ! u t o 0 r e c h a r g e t o b a n k n i s i n t e r r u p t e d b y s u b s e q u e n t 7 r i t e t o b a n k m $ o n g t # a r e # , + t 20 b a n k n t 7 2 b a n k n # o m m a n d . / 0 . / 0 . / 0 7 2 ) 4 % . / 0 7 2 ! 0 . / 0 . / 0 ! d d r e s s " a n k n # o l b " a n k m # o l x $ 1 $ ) b $ ) b $ ) x $ ) x $ ) x $ ) x
data sheet 34 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4.9 auto refresh and self refresh the mobile-ram requires a refresh of a ll rows in a rolling interval. each refr esh is generated in one of two ways: by an explicit auto refresh command, or by an internally timed event in self refresh mode. 2.4.9.1 auto refresh figure 41 auto refresh command auto refresh is used during normal operation of the mobile-ram. the command is non persistent, so it must be issued each time a refresh is required. a minimum row cycle time ( t rc ) is required between two auto refresh commands. th e same rule applies to any access command after the auto refresh operation. all banks must be precharged prior to the auto refresh command. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the mobile-ram requires auto refresh cycles at an average periodic interval of 7.8 s (max.). partial array mode has no influence on auto refresh mode. figure 42 auto refresh $ o n g t # a r e # 3 # + % ( i g h # , + ! ! " ! " ! # ! 3 7 % 2 ! 3 " a ! 2 o w n b a n k ! r o w n t 2 0 t 2 # t 2 # $ o n g t # a r e $ 1 ( i g h : ! ! 0 2 o w n 0 r e ! l l ! d d r e s s " a ! 2 o w n # o m m a n d . / 0 ! 2 & . / 0 . / 0 . / 0 . / 0 0 2 % ! 2 & ! # 4 # , +
data sheet 35 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4.9.2 self refresh figure 43 self refresh entry command the self refresh command can be used to retain data in the mobile-ram, even if the rest of the system is powered down. when in the self refresh mode, the mobile-ram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is low. input signals except cke are ?don?t care? during self refresh. the procedure for exiting self refresh requires a stable clock prior to cke returning high. once cke is high, nop commands must be issued for t rc because time is required for a completion of any internal refresh in progress. if during normal operation burst auto refresh or user controlled refresh is used, add 8192 auto refresh cycles just before self refresh entry and just after self refresh exit. figure 44 self refresh entry and exit $ o n g t # a r e # 3 # + % # , + ! ! " ! " ! # ! 3 7 % 2 ! 3 table 13 timing parameters for auto refresh and self refresh parameter symbol - 7.5 units notes min. max. active to active command period t rc 67 ? ns 1) 1) these parameters account for the number of clock c ycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. precharge command period t rp 19 ? ns 1) refresh period (8192 rows) t ref ?64ms 1) self refresh exit time t srex 1? t ck 1) t 2 0 t 2 # t 2 # 3 e l f 2 e f r e s h % n t r y # o m m a n d 3 e l f 2 e f r e s h % x i t # o m m a n d % x i t f r o m 3 e l f 2 e f r e s h ! n y # o m m a n d ! u t o 2 e f r e s h 2 e c o m m e n d e d $ o n g t # a r e t 3 2 % 8 ! ! 0 0 r e ! l l 2 o w n # , + # + % # o m m a n d . / 0 ! 2 & . / 0 . / 0 . / 0 0 2 % ! 2 & ! # 4 . / 0 ! d d r e s s " a ! 2 o w n $ 1 ( i g h :
data sheet 36 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.4.10 power down figure 45 power down entry command power-down is entered when cke is registered low (no accesses can be in progress). if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding clk and cke. cke low must be maintained during power- down. power-down duration is limited by the refresh requirements of the device ( t ref ). the power-down state is synchronously exited when cke is registered high (along with a nop or deselect command). one clo ck delay is required for power down entry and exit. figure 46 power down entry and exit 2.4.10.1 deep power down the deep power down mode is an unique function on low power sdram devices wit h extremely low current consumption. deep power down mode is en tered using the burst terminate command (cf. figure 35 ) except that cke is low. all internal voltage generators inside the device are stopped and all memory data is lost in this mode. to enter the deep power down mode all banks must be precharged. the deep power down mode is asynchronously exited by asserting cke high. after the exit, the same command sequence as for power-up initialization, including the 200 s initial pause, has to be applied before any other command may be issued (cf. figure 3 and figure 4 ). $ o n g t # a r e # 3 # + % # , + 2 ! 3 ! ! " ! " ! 7 % # ! 3 $ o n g t # a r e 0 r e c h a r g e 0 o w e r $ o w n m o d e s h o w n a l l b a n k s a r e i d l e a n d t 2 0 m e t w h e n 0 o w e r $ o w n % n t r y # o m m a n d i s i s s u e d ! n y # o m m a n d 0 o w e r $ o w n % n t r y t 2 0 % x i t f r o m 0 o w e r $ o w n ( i g h : $ 1 ! ! 0 6 a l i d 0 r e ! l l ! d d r e s s 6 a l i d # o m m a n d . / 0 . / 0 . / 0 6 a l i d 0 2 % # + % # , +
data sheet 37 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 2.5 function truth tables table 14 current state bank n - command to bank n current state cs ras cas we command / action notes any h x x x deselect (nop / cont inue previous operation) 1)2)3)4)5)6) 1) this table applies when cken-1 was high and cken is high and after t rc has been met (if the previous state was self refresh). 2) this table is bank-specific, except where noted, i.e., the cu rrent state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto pr echarge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto pr echarge disabled, and has not yet terminated or been terminated. 4) the following states must not be interrupted by a comm and issued to the same bank. deselect or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and according to table 15 . precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank is in the ?idle? state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank is in the ?row active? state. read with ap enabled: starts with registration of a read co mmand with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write with ap enabled: starts with registration of a write co mmand with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. l h h h no operation (nop / continue previous operation) 1) to 6) idle l l h h active (select and activate row) 1) to 6) lllhauto refresh 1) to 7) llllmode register set 1) to 7) l l h l precharge 1) to 6), 8) row active l h l h read (select column and start read burst) 1) to 6), 9) l h l l write (select column and start write burst) 1) to 6), 9) l l h l precharge (deactivate row in bank or banks) 1) to 6), 10) read (auto- precharge disabled) l h l h read (select column and start new read burst) 1) to 6), 9) l h l l write (select column and start new write burst) 1) to 6), 9) l l h l precharge (truncate read burst, start precharge) 1) to 6), 10) l h h l burst terminate 1) to 6), 11) write (auto- precharge disabled) l h l h read (select column and start read burst) 1) to 6), 9) l h l l write (select column and start write burst) 1) to 6), 9) l l h l precharge (truncate write burst, start precharge) 1) to 6), 10) l h h l burst terminate 1) to 6), 11)
data sheet 38 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 5) the following states must not be inte rrupted by any executable command; deselect or nop commands must be applied on each positive clock edge during these states. refreshing: starts with regi stration of an auto refresh command and ends when t rc is met. once t rc is met, the sdram is in the ?all banks idle? state. accessing mode register: starts with registration of a mo de register set command and ends when t mrd has been met. once t mrd is met, the sdram is in the ?all banks idle? state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks are in the idle state. 6) all states and sequences not shown are illegal or reserved. 7) not bank-specific; requires that all banks are idle and no bursts are in progress. 8) same as nop command in that state. 9) reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 10) may or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 11) not bank-specific; burst terminat e affects the most recent read or write burst, regardless of bank. table 15 current state bank n - command to bank m (different bank) current state cs ras cas we command / action notes any h x x x deselect (nop / cont inue previous operation) 1)2)3)4)5)6) 1) this table applies when cken-1 was high and cken is high and after t rc has been met (if the previous state was self refresh). 2) this table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming th at bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. l h h h no operation (nop / continue previous operation) 1) to 6) idle xxxxany command otherwise allowed to bank n 1) to 6) row activating, active, or precharging l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7) l h l l write (select column and start write burst) 1) to 7) l l h l precharge (deactivate row in bank or banks) 1) to 6) read (auto- precharge disabled) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7) l h l l write (select column and start write burst) 1) to 8) l l h l precharge (deactivate row in bank or banks) 1) to 6) write (auto- precharge disabled) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7) l h l l write (select column and start write burst) 1) to 7) l l h l precharge (deactivate row in bank or banks) 1) to 6) read (with auto- precharge) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7), 9) l h l l write (select column and start write burst) 1) to 9) l l h l precharge (deactivate row in bank or banks) 1) to 6) write (with auto- precharge) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7), 9) l h l l write (select column and start write burst) 1) to 7), 9) l l h l precharge (deactivate row in bank or banks) 1) to 6)
data sheet 39 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram functional description 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto pr echarge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto pr echarge disabled, and has not yet terminated or been terminated. read with ap enabled: starts with registration of a read co mmand with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write with ap enabled: starts with registration of a write co mmand with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. 4) auto refresh, self refresh and mode register set commands may only be issued when all banks are idle. 5) a burst terminate command cannot be issued to another bank; it applies to the bank repres ented by the current state only. 6) all states and sequences not shown are illegal or reserved. 7) reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8) requires appropriate dqm masking. 9) concurrent auto precharge: bank n will start precharging when its burst has been interrupted by a read or write command to bank m. table 16 truth table - cke cken-1 cken current state command action notes l l power down x maintain power down 1)2)3)4) 1) cken is the logic state of cke at clock edge n; c ken-1 was the state of cke at the previous clock edge. 2) current state is the state immediately prior to clock edge n. 3) command n is the command registered at cloc k edge n; action n is a result of command n. 4) all states and sequences not shown are illegal or reserved. self refresh x maintain self refresh 1) to 4) clock suspend x main tain clock suspend 1) to 4) deep power down x maintain deep power down 1) to 4) l h power down deselect or nop exit power down 1) to 4) self refresh deselect or nop exit self refresh 1) to 5) 5) deselect or nop commands should be issued on any clock edges occurring during t rc period. clock suspend x exit clock suspend 1) to 4) deep power down x exit deep power down 1) to 4), 6) 6) exit from deep power down requires the same command sequence as for power-up initialization. h l all banks idle deselect or nop enter precharge power down 1) to 4) bank(s) active deselect or nop enter active power down 1) to 4) all banks idle auto refresh enter self refresh 1) to 4) read / write burst (valid) enter clock suspend 1) to 4) hh see table 14 and table 15 1) to 4)
data sheet 40 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram electrical characteristics 3 electrical characteristics 3.1 operating conditions attention: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; ex ceeding only one of these values may cause irreversible damage to the integrated circuit. table 17 absolute maximum ratings parameter symbol values unit min. max. power supply voltage v dd -0.3 2.7 v power supply voltage for output buffer v ddq -0.3 2.7 v input voltage v in -0.3 v ddq + 0.3 v output voltage v out -0.3 v ddq + 0.3 v operation case temperature commercial t c 0+70 c extended -25 +85 c storage temperature t stg -55 +150 c power dissipation p d ?0.7w short circuit output current i out ?50ma table 18 pin capacitances 1)2) 1) these values are not subject to production test but verified by device characterization. 2) input capacitance is measured according to jep147 with vdd, vddq applied and all other pins (except the pin under test) floating. dq?s should be in high impedance state. this may be achieved by pulling cke to low level. parameter symbol values unit min. max. input capacitance: clk c i1 1.5 3.0 pf input capacitance: all other input pins c i2 1.5 3.0 pf input/output capacitance: dq c io 3.0 5.0 pf
data sheet 41 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram electrical characteristics table 19 electrical characteristics 1) 1) 0 c t c 70 c (comm.), -25 c t c 85 c (ext.); all voltages referenced to v ss . v ss and v ssq must be at same potential. parameter symbol values unit notes min. max. power supply voltage v dd 1.70 1.95 v ? power supply voltage for dq output buffer v ddq 1.70 1.95 v ? input high voltage v ih 0.8 v ddq v ddq + 0.3 v 2) 2) v ih may overshoot to v dd + 0.8 v for pulse width < 4 ns; v il may undershoot to -0.8 v for pulse width < 4 ns. pulse width measured at 50% with amplitude me asured between peak voltage and dc reference level. input low voltage v il -0.3 0.3 v 2) output high voltage ( i oh = -0.1 ma) v oh v ddq - 0.2 ? v ? output low voltage ( i ol = 0.1 ma) v ol ?0.2v? input leakage current i il -1.0 1.0 a? output leakage current i ol -1.5 1.5 a?
data sheet 42 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram electrical characteristics 3.2 ac characteristics table 20 ac characteristics 1)2)3)4) 1) 0 c t c 70 c (comm.), -25 c t c 85 c (ext.) ; v dd = v ddq = 1.70v to 1.95v; 2) all parameters assumes proper device initialization. 3) ac timing tests measured at 0.9 v. 4) the transition time t t is measured between v ih and v il ; all ac characteristics assume t t = 1 ns. parameter symbol - 7.5 unit notes min. max. clock cycle time cl = 3 t ck 7.5 ? ns ? cl = 2 9.5 ? ns clock frequency cl = 3 f ck ?133mhz? cl = 2 ? 105 mhz access time from clk cl = 3 t ac ?5.4ns 5)6) 5) specified t ac and t oh parameters are measured with a 30 pf capacitive load only as shown below: 6) if t t (clk) > 1 ns, a value of ( t t /2 - 0.5) ns has to be added to this parameter. cl = 2 ? 6.0 ns clock high-level width t ch 2.5 ? ns ? clock low-level width t cl 2.5 ? ns ? address, data and command input setup time t is 1.5 ? ns 7) 7) if t t > 1 ns, a value of [0.5 x ( t t - 1)] ns has to be added to this parameter. address and command input hold time t ih 0.5 ? ns 7) data (dq) input hold time 0.8 ? mode register set command period t mrd 2? t ck ? dq low-impedance time from clk t lz 1.0 ? ns ? dq high-impedance time from clk t hz 3.0 7.0 ns ? data out hold time t oh 2.5 ? ns 5)6) dqm to dq high-z delay (read commands) t dqz ?2 t ck ? dqm write mask latency t dqw 0? t ck ? active to active command period t rc 67 ? ns 8) 8) these parameter account for the number of clock cycl es and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period; round up to next integer. active to read or write delay t rcd 19 ? ns 8) active bank a to active bank b delay t rrd 15 ? ns 8) active to precharge command period t ras 45 100k ns 8) write recovery time t wr 14 ? ns 9) 9) the write recovery time of t wr = 14 ns allows the use of one clock cycle for the write re covery time when f ck 72 mhz. with f ck > 72 mhz two clock cycles for t wr are mandatory. qimonda recommends to use two clock cycles for the write recovery time in all applications. precharge command period t rp 19 ? ns 8) refresh period (8192 rows) t ref ?64ms? self refresh exit time t srex 1? t ck ? 30 pf i/o
data sheet 43 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram electrical characteristics 3.3 operating currents table 21 maximum op erating currents 1) 1) 0 c t c 70 c (comm.), -25 c t c 85 c (ext.) ; v dd = v ddq = 1.70v to 1.95v; recommended operating conditions unless otherwise noted parameter & test conditions symbol hy[b/e]256 160b[c/f]x unit note - 7.5 operating current: one bank: active / read / precharge, bl = 1, t rc = t rcmin i dd1 60 ma 2)3) 2) these values are measured with t ck = 7.5 ns 3) all parameters are measured with no output loads. precharge power-down standby current: all banks idle, cs v ihmin , cke v ilmax , inputs changing once every two clock cycles i dd2p 2.4 ma 2) precharge power-down standby current with clock stop: all banks idle, cs v ihmin , cke v ilmax , all inputs stable i dd2ps 2.3 ma ? precharge non power-down standby current: all banks idle, cs v ihmin , cke v ihmin , inputs changing once every two clock cycles i dd2n 13 ma 2) precharge non power-down standby current with clock stop: all banks idle, cs v ihmin , cke v ihmin , all inputs stable i dd2ns 2.5 ma ? active power-down standby current: one bank active, cs v ihmin , cke v ilmax , inputs changing once every two clock cycles i dd3p 4.2 ma 2) active power-down standby current with clock stop: one bank active, cs v ihmin , cke v ilmax , all inputs stable i dd3ps 4.0 ma ? active non power-down standby current: one bank active, cs v ihmin , cke v ihmin , inputs changing once every two clock cycles i dd3n 16 ma 2) active non power-down standby current with clock stop: one bank active, cs v ihmin , cke v ihmin , all inputs stable i dd3ns 3.4 ma ? operating burst read current: all banks active; continuous burst read, inputs changing once every two clock cycles i dd4 45 ma 2)3) auto-refresh current: t rc = t rcmin , ?burst refresh?, inputs changing once every two clock cycles i dd5 100 ma 2) self refresh current: self refresh mode, cs v ihmin , cke v ilmax , all inputs stable i dd6 2.5 ma ? deep power down current i dd7 10 a 4) 4) value shown as typical.
data sheet 44 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram package outlines 4 package outlines figure 47 p-vfbga-54-2 (very low profile fine pitch ball grid array package) b 4) a 4) 8 x 0.8 = 6.4 0.8 +0.01 0.12 -0.04 20? ?? 2) 1) 3) d 5) 1.7 ?.03 d 0.3 0.8 8 x 0.8 = 6.4 seating plane c c 0.1 c 0.1 -0.2 1.0 0.31 ?.03 a 54x 0.41 ?.03 ?.07 ?.12 c m m b 5) middle of ball matrix 4) middle of packages edges 2) die sort fiducial 3) bad unit marking (bum) 1) a1 marking ballside 1.5 12 4.25 2.24 8 2) 0.2
data sheet 45 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram list of figures figure 1 standard ballout 256-mbit mobile-ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3 power-up sequence and mode register sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4 state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5 address / command inputs timing para meters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 no operation command 14 mode register set command 15 figure 8 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 active command 16 figure 10 bank activate timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 read command 17 figure 12 basic read timing parameters for dqs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13 single read burst (cas latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 14 single read burst (cas latency = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 15 consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 16 random read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17 non-consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 18 terminating a read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 19 clock suspend mode for r ead bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 20 read burst - dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 21 read to write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 22 read to precharge timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 write command 24 figure 24 basic write timing parameters for dqs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 25 write burst (cas latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 26 write burst (cas latency = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 27 consecutive write bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 28 random write bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 29 non-consecutive write bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 30 terminating a write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 31 clock suspend mode for write bursts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 32 write burst - dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 33 write to read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 34 write to precharge timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 burst terminate command 30 precharge command 31 figure 37 read with auto precharge interrupted by read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 38 read with auto precharge interrupted by write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 39 write with auto precharge interrupted by read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 40 write with auto precharge interrupted by write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 auto refresh command 34 figure 42 auto refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 self refresh entry command 35 figure 44 self refresh entry and exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 power down entry command 36 figure 46 power down entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 47 p-vfbga-54-2 (very low profile fi ne pitch ball grid array pa ckage) . . . . . . . . . . . . . . . . . . . . . 44
data sheet 1 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram table 1 performance 3 table 2 memory addressing scheme 3 table 3 ordering information 4 table 4 pin description 6 table 5 burst definition 9 table 6 command overview 13 table 7 inputs timing parameters 14 table 8 timing parameters for mode register set command 15 table 9 timing parameters for active command 16 table 10 timing parameters for read 18 table 11 timing parameters for write 25 table 12 timing parameters for precharge 31 table 13 timing parameters for au to refresh and self refresh 35 table 14 current state bank n - command to bank n 37 table 15 current state bank n - command to bank m (different bank) 38 table 16 truth table - cke 39 table 17 absolute maximum ratings 40 table 18 pin capacitances 40 table 19 electrical characteristics 41 table 20 ac characteristics 42 table 21 maximum operating currents 43
data sheet 2 rev. 1.11, 2007-01 07142005-cr47-rb2e hy[b/e]18l256160b[c/f]x-7.5 256-mbit mobile-ram table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 pin definition and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 power on and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1.1 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.1.2 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1.3 read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1.4 write burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1.5 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1.6 partial array self refresh (pasr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1.7 temperature compensated self refresh (tcsr) with on-chip temperature sensor . . . . . . . . 11 2.2.1.8 selectable drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4.1 no operation (nop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.2 deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.3 mode register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.4 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.5 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.5.1 read burst termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.5.2 clock suspend mode for read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.5.3 read - dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.5.4 read to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.5.5 read to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4.6 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.6.1 write burst termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4.6.2 clock suspend mode for write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.6.3 write - dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4.6.4 write to read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4.6.5 write to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.4.7 burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.4.8 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4.8.1 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4.8.2 concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.9 auto refresh and self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.9.1 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.9.2 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4.10 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.10.1 deep power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.5 function truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3 operating currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
edition 2007-01 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this data sheet shall in no event be regarded as a guarantee of co nditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. under no circumstances may the qimonda product as referred to in this data sheet be used in 1. any applications that are intended for military usage (including but not limited to weaponry), or 2. any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices an d systems collectively referred to as "critical systems"), if a) a failure of the qimonda product can reasonable be expected to - directly or indirectly - (i) have a detrimental effect on such critical systems in terms of reliability, effectiveness or safety; or (ii) cause the failure of such critical systems; or b) a failure or malfunction of such critical systems ca n reasonably be expected to - directly or indirectly - (i) endanger the health or the life of the user of such critical systems or any other person; or (ii) otherwise cause material damages (including but not lim ited to death, bodily injury or significant damages to property, whether tangible or intangible). www.qimonda.com data sheet,

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